Conventionally, an asperity of a substrate surface on which a semiconductor device is formed is represented by using a statistic index, such as an average surface roughness (Ra) (Patent Document 1). Those values, such as 0.02 nm, 0.07 nm, 0.09 nm, and 0.11 nm, which are unrelated to surface atoms are used as the index. This is because there has been no technique of industrially flattening a semiconductor substrate surface at an atomic level and surface flattening has been performed by isotropic oxidation or the like (Non-Patent Document 1).
In the conventional method, it is impossible, in principle, to eliminate the asperity at the atomic level and, as a result, degradation in carrier mobility is induced in a semiconductor device due to a surface asperity (Non-Patent Documents 2 and 3). Meanwhile, as regards flattening of a silicon substrate surface, it is reported that the substrate surface inclined by approximately 4 degrees from a silicon crystal plane (100) is flattened at the atomic level by oxidation and etching with a strongly-acid solution with respect to a substrate surface (Non-Patent Document 4). It is also proposed that a (110) plane or a plane inclined from the (110) plane is flattened at the atomic level and provided with a step at the atomic level (Patent Document 2).
In the above-mentioned prior documents, no description is made about the problem addressed by the present invention and the means to solve the problem. The above-mentioned prior documents do not disclose a semiconductor substrate and a semiconductor device, in which steps and terraces are controlled in direction and width throughout a substantially entire area of the substrate surface to suppress degradation in carrier mobility due to the surface asperity.    Patent Document 1: JP-A-2004-356114    Patent Document 2: JP-A-2004-265918    Non-Patent Document 1: A. Teramoto et al., “Very High Carrier Mobility for High-Performance CMOS on a Si(110) Surface,” IEEE Electron Devices, Vol. 54, No. 6, pp. 1438-1445, June 2007.    Non-Patent Document 2: S. Takagi et al., “On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration,” IEEE Electron Devices, Vol. 41, No. 12, pp. 2357-2362, December 1994.    Non-Patent Document 3: T. Ohmi et al., “Revolutional Progress of Silicon Technologies Exhibiting Very High Speed Performance Over a 50-GHz Clock rate,” IEEE Electron Devices, Vol. 54, No. 6, pp. 1471-1477, June 2007.    Non-Patent Document 4: Y. Morita et al., “Atomic scale flattening and hydrogen termination of the Si(001) surface by wet-chemical treatment,” J. Vac. Sci. Technol. A, Vac. Surf. Film, Vol. 14, No. 3, pp. 854-858, May 1996.    Non-Patent Document 5: T. Ohmi, “Total room temperature wet cleaning Si substrate surface,” J. Electrochem. Soc., Vol. 143, No. 9, pp. 2957-2964, September 1996.